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IP与芯片架构创新中心曾晓洋论文合集

1、Y. Li, C. Chen, X.   Cheng, J. Han and X. Zeng, "DMBF: Design Metrics Balancing Framework for   Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization,"   in IEEE Transactions on   Circuits and Systems I: Regular Papers, vol. 70, no. 10, pp.   4015-4027, Oct. 2023.

2W. Chen, Y. Huang,   M. Wang, X. Wu and X. Zeng, "TSDN: Two-Stage Raw Denoising in the   Dark," in IEEE Transactions on Image Processing, vol. 32, pp. 3679-3689,   2023.

3 Z. Li, Z. Chen, J.   Wang, J Jiang, S Du, X Cheng, X Zeng, J Han., "A Self-Bias-Flip With   Charge Recycle Interface Circuit With No External Energy Reservoir for   Piezoelectric Energy Harvesting Array," in IEEE Transactions on Power   Electronics, Vol. 38, No. 9, pp. 11630-11641, Sept. 2023.

4Y. Huang et al.,   "LineDL: Processing Images Line-by-Line With Deep Learning," in   IEEE Transactions on Image Processing, Vol. 32, pp. 3150-3162, 2023.

5D. Lu, X. Zeng and   Z. Hong, "Accurate Loop Gain Model of Ripple-Based Constant on-time   Controlled Buck Converters," in IEEE Transactions on Power Electronics, Vol.   38, no. 6, pp. 7034-7048, June 2023.

6P. Xu et al.,   "A 2.7 W AC-Coupled Hybrid Supply Modulator Achieving 200 MHz   Envelope-Tracking Bandwidth for 5G New Radio Power Amplifier," in IEEE   Transactions on Power Electronics, vol. 38, no. 6, pp. 7416-7427, June 2023.

7Z. Hao, H. Sun, G.   Xiang, P. Zhang, X. Zeng and Y. Fan, "A Reconfigurable Multiple   Transform Selection Architecture for VVC," in IEEE Transactions on Very   Large Scale Integration (VLSI) Systems, vol. 31, no. 5, pp. 658-669, May 2023.

8Z. Guo et al.,   "An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and   Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge   Devices," in IEEE Transactions on Circuits and Systems II: Express   Briefs, vol. 70, no. 7, pp. 2645-2649, July 2023.

9Y. Liu, Y. Li, X.   Cheng, J. Han and X. Zeng, "A Non-Redundant Latch With Key-Node-Upset   Obstacle of Beneficial Efficiency for Harsh Environments Applications,"   in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no.   4, pp. 1639-1648, April 2023.

10T. Qu, L. Liu, X.   Zeng, Z. Hong and J. Xu, "A 0.24-μV-Input-Ripple 8-μV-Input-Offset   10-MHz Chopper Operational Amplifier Employing MOS-DAC-Based Offset Calibration,"   in IEEE Solid-State Circuits Letters, vol. 6, pp. 17-20, 2023.

11T. Qu, Q. Pan, L.   Liu, X. Zeng, Z. Hong and J. Xu, "A 1.8–GΩ Input-Impedance 0.15–μV   Input-Referred–Ripple Chopper Amplifier With Local Positive Feedback and   SAR-Assisted Ripple Reduction," in IEEE Journal of Solid-State Circuits,   vol. 58, no. 3, pp. 796-805, March 2023.

12H. Zhao, C. Fan,   Z. Chen, P. Zheng, X. Zeng and Z. Hong, "A Tuning Range Extension   Technique for Waveform-Shaping Single-Core CMOS Oscillators With No Dedicated   Harmonic Tuning," in IEEE Transactions on Circuits and Systems II:   Express Briefs, vol. 70, no. 4, pp. 1306-1310, April 2023.

13X. Zhang et al.,   "Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read   Performance," in IEEE Transactions on Circuits and Systems II: Express   Briefs, vol. 70, no. 6, pp. 2226-2230, June 2023.

14Y. Qiu, J. Jiao,   X. Zeng and Y. Fan, "Tag-Sharer-Fusion Directory: A Scalable Coherence   Directory With Flexible Entry Formats," in IEEE Transactions on Parallel   and Distributed Systems, vol. 34, no. 1, pp. 262-274, 1 Jan. 2023.

15C. Zhao, J. Fang,   J. Jiang, X. Xue and X. Zeng, "ARBiS: A Hardware-Efficient SRAM CIM CNN   Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance   Charge Sharing for AI Edge Application," in IEEE Transactions on   Circuits and Systems I: Regular Papers, vol. 70, no. 1, pp. 364-377, Jan.   2023.

16D. Chen et al.,   "A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division   and Capacitive Coupling for CNN Acceleration in AI Edge Applications,"   in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no.   1, pp. 276-280, Jan. 2023.



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2023-10-23 14:31

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